1. Field of the Invention
The present invention relates to the field of semiconductor manufacture, and particularly to a transistor and a method for forming the same.
2. Description of Prior Art
Stress Memorization Technique (SMT) and Stress-contact etch stop layer (CESL) are two solutions to promote transistor carrier mobility currently. By virtue of the two solutions, stable stress is formed in a trench of a transistor for promoting carrier mobility in the trench. The stress is parallel to length of the trench, and may be tensile stress or compressive stress. In general, the tensile stress may loosen the atomic arrangement in the trench for promoting mobility of electrons, and is adapted for NMOS transistor. The compressive stress may tighten the atomic arrangement in the trench for promoting mobility of holes, and is adapted for PMOS transistor.
FIGS. 1-3 exemplarily show a conventional method for forming a transistor.
As shown in FIG. 1, a semiconductor substrate 10 is provided. An NMOS transistor and a PMOS transistor are formed in the substrate 10. Isolations 11 are defined between the NMOS transistor and the PMOS transistor. The NMOS transistor includes P well (not shown), an NMOS transistor gate 13, and NMOS transistor source/drain regions 12 in the P well and at opposite sides of the NMOS transistor gate 13. The PMOS transistor includes N well (not shown), a PMOS transistor gate 15, and PMOS transistor source/drain regions 14 in the N well and at opposite sides of the PMOS transistor gate 15.
As shown in FIG. 2, a stress layer 16 is formed on the NMOS transistor and the PMOS transistor for covering the NMOS transistor source/drain regions 12, the NMOS transistor gate 13, the PMOS transistor source/drain regions 14, the PMOS transistor gate 15, and the substrate 10. The stress layer 16 has material of silicon nitride, and has tensile stress or compressive stress.
As shown in FIG. 3, the stress layer 16 on the PMOS transistor source/drain regions 14 and the PMOS transistor gate 15 is removed, while the stress layer 16 on the NMOS transistor source/drain regions 12 and the NMOS transistor gate 13 is remained. The stress layer 16 on the NMOS transistor source/drain regions 12 and the NMOS transistor gate 13 is annealed for providing tensile stress for the NMOS transistor. Thus carrier (electrons) mobility in the NMOS transistor trench may be promoted. After annealing, the stress layer 16 on the NMOS transistor source/drain regions 12 and the NMOS transistor gate 13 is removed by etching.
By the conventional method for forming a transistor, saturation current of the transistor is too low. It is desired to address this issue.